1. Field of the Invention
The present invention relates to a method of correcting a mask layout, and more particularly, to a method of correcting systematic errors produced during a pattern transfer process on a mask layout.
2. Description of the Prior Art
To form a designed integrated circuit (IC) on a semiconductor wafer, a semiconductor foundry forms a mask with a designed layout pattern and then performs a photolithographic process to transfer the designed layout pattern on the mask to a photoresist layer positioned on a semiconductor wafer. Following this, an etching process is performed using the photoresist layer as an etching mask, transferring patterns of the photoresist layer to the semiconductor wafer. The photolithographic process and the etching process are the most important steps for determining the IC patterns during the semiconductor manufacturing process.
However, during the photolithographic process, a pattern transferring deviation occurs due to an overexposure or an underexposure at corners of the closely arranged mask patterns. As Being non-uniformly exposed, an optical proximity effect occurs, to affecting the pattern transferring precision on the photoresist layer. To prevent the optical proximity effect from affecting the pattern transferring precision, a solution is using to use a computer aided design (CAD) system to provide an optical proximity correction (OPC) on the mask patterns.
Furthermore, a pattern transferring deviation also occurs in the etching process since it is believed that different pattern densities of the IC elements induce a micro-loading effect. Therefore, a method for improving an etching uniformity on a semiconductor wafer is required.
Please refer to FIG. 1, which shows a mask layout according to the prior art. The mask layout includes a plurality of linear element patterns A, B, and C for defining conductive areas, such as word lines or bit lines. The element patterns A, B, and C have an equal line width w. A line space s between two element patterns A is defined as a, a line space s between two element patterns B is defined as b, and a line space s between two element patterns C is defined as c. The line spaces a, b, and c are not equal, and the pattern densities of the element patterns A, B, and C on the mask layout are therefore considered different.
Next, please refer to FIG. 2, which shows a relationship between an etched line width w and a line space s between the element patterns on the mask layout. The vertical axis of the relation diagram represents an after-etch-inspection (AEI) critical dimension of an element pattern's line width, The horizontal axis of the relation diagram represents a line space between two element patterns of the mask layout. The circles represent experimental values of the etched line width, and the solid line represents a fitting curve of the experimental values of the etched line width. As shown in FIG. 2, since a value of the etched line width w changes as a result of a micro-loading effect or other systematic errors, different etched line widths w are achieved for the element patterns having different pattern densities. For example, when the etched line width increases with an increase in the line space between two adjacent element patterns, a greater etched line width is achieved for the isolated element patterns, and a narrower etched line width is achieved for the dense element patterns.
For an integrated circuit with design rules of 0.18 μm, micro-loading effect is mildly regarded slight since it is not a subject factor to affect etching uniformity of a semiconductor wafer. However, when the design rules of the semiconductor elements lower to 0.15 μm, 0.13 μm, or even 0.1 μm, a 10 nm line width deviation creates an error percentage of 6%, 8%, or even 10%. Therefore, improvement in surface uniformity has become an important issue for the manufacturing process, especially for the design rules of below 0.15 μm.